HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 421

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination
with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the
input capture input detected edge.
The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3).
ICE Bit in
8TCSR1
(8TCSR3)
0
1
Bits 1 and 0—Output Select A1 and A0 (OS1, OS0): These bits select the compare match A
output level.
Bit 1
OS1
0
1
Rev. 2.0, 06/04, page 392 of 980
When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
When the compare match register function is used, the timer output priority order is: toggle
output > 1 output > 0 output.
If compare match A and B occur simultaneously, the output changes in accordance with the
higher-priority compare match.
When bits OIS3, OIS2, OS1, and OS0 are all cleared to 0, timer output is disabled.
Bit 0
OS0
0
1
0
1
Bit 3
OIS3
0
1
0
1
Bit 2
OIS2 Description
0
1
0
1
0
1
0
1
Description
No change when compare match A occurs
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A occurs (toggle output)
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B occurs (toggle output)
TCORB input capture on rising edge
TCORB input capture on falling edge
TCORB input capture on both rising and falling edges
(Initial value)
(Initial value)

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