HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 570

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6. If an error signal is sent back from the receiving device after transmission of one frame is
7. The TEND bit in SSR is not set for the frame for which the error signal was received.
8. If an error signal is not sent back from the receiving device, the ERS flag is not set in SSR.
9. If an error signal is not sent back from the receiving device, transmission of one frame,
Support of Block Transfer Mode: The smart card interface of this LSI supports an IC card
(smart card) interface corresponding to T=0 (character transfer) in ISO/IEC 7816-3.
Ds
Retransmission when SCI is in Transmit Mode
Figure 14.13 illustrates retransmission when the SCI is in transmit mode.
completed, the ERS bit is set to 1 in SSR. If the RIE bit in SCR is set to the enable state, an
ERI interrupt is requested. The ERS bit should be cleared to 0 in SSR before the next parity bit
sampling timing.
including retransmission, is assumed to have been completed, and the TEND bit is set to 1 in
SSR. If the TIE bit in SCR is set to the enable state, a TXI interrupt is requested. If TXI is
enabled as a DMA transfer activation source, the next data can be written in TDR
automatically. When the DMAC writes data in TDR, the TDRE bit is automatically cleared to
0.
RDRF
PER
Ds
TDRE
TEND
ERS
Transfer from TDR to TSR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Frame n
Frame n
Figure 14.13 Retransmission in SCI Transmit Mode
Figure 14.12 Retransmission in SCI Receive Mode
[6]
[2]
[1]
[7]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransmitted frame
Retransmitted frame
(DE)
Rev. 2.0, 06/04, page 541 of 980
[8]
[9]
(DE)
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
[4]
[3]
Ds D0 D1 D2 D3 D4
Frame n+1
Frame n+1