HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 734

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
20.4
20.4.1
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The DMAC and on-chip supporting
modules are reset and halted. As long as the specified voltage is supplied, however, CPU register
contents and on-chip RAM data are retained. The settings of the I/O ports and DRAM interface*
are also held. When the WDT is used as a watchdog timer (WT/IT = 1), the TME bit must be
cleared to 0 before setting SSBY. Also, when setting TME to 1, SSBY should be cleared to 0.
Clear the BRLE bit in BRCR (inhibiting bus release) before making a transition to software
standby mode.
Note: * RTCNT and bits 7 and 6 of RTMCSR are initialized. Other bits and registers hold their
20.4.2
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ
IRQ
Exit by Interrupt: When an NMI, IRQ
clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0
in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ
CPU.
Exit by RES
supplied immediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY
2
pin, or by input at the RES or STBY pin.
previous states.
RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
RES
RES
STBY
STBY
STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
Software Standby Mode
Transition to Software Standby Mode
Exit from Software Standby Mode
0
, IRQ
1
, and IRQ
2
are cleared to 0, or if these interrupts are masked in the
0
, IRQ
1
, or IRQ
2
interrupt request signal is received, the
Rev. 2.0, 06/04, page 705 of 980
0
, IRQ
1
, or

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