HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 191

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.8
In a DRAM access cycle, wait states can be inserted (1) between the T
between the T
Insertion of T
by setting the RCW bit to 1 in DRCRB.
Insertion of T
area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the T
state and T
Figure 6.20 shows an example of the timing for wait state insertion.
Rev. 2.0, 06/04, page 162 of 980
Read access
Write access
Note: n = 2 to 5
Wait Control
c2
Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB)
state by means of settings in WCRH and WCRL.
c1
rw
w
(
state and T
(
Wait State(s) between T
Wait State between T
PB
PB
4
4
D
D
A
/PB
/
/PB
/
15
15 to
23
(
(
(
to D
5
to A
5
D
c2
)
)
)
0
)
0
0
)
state.
T
r
p1
and T
c1
and T
c1
: One T
c2
T
: When the bit in ASTCR corresponding to an
p2
rw
state can be inserted between T
High level
High level
Row
Tr
r
state and T
Column
T
c1
c1
state, and (2)
T
c2
r
and T
c1
c1