HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 93

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS
outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1
SSOE
0
1
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
0
1
3.4
3.4.1
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2
Ports 1, 2, and 5 function as address pins A
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3
Ports 1, 2, 5, and part of port A function as address pins A
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A
(BRCR). (In this mode A
Rev. 2.0, 06/04, page 64 of 980
23
Operating Mode Descriptions
Mode 1
Mode 2
Mode 3
Description
In software standby mode, the address bus and bus control signals are all high-
impedance
signals are fixed high
Description
On-chip RAM is disabled
On-chip RAM is enabled
In software standby mode, the address bus retains its output state and bus control
to A
21
are valid when 0 is written in bits 7 to 5 of the bus release control register
0
to CS
20
is always used for address output.)
7
, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as
19
19
to A
to A
0
0
, permitting access to a maximum 1-Mbyte
, permitting access to a maximum 1-Mbyte
23
to A
0
, permitting access to a
(Initial value)
(Initial value)

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