HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 207

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Example of Program Setup Procedure: Figure 6.34 shows an example of the program setup
procedure.
6.5.13
Note the following points when using the DRAM refresh function.
Rev. 2.0, 06/04, page 178 of 980
Refresh cycles will not be executed when the external bus released state, software standby
mode, or a bus cycle is extended by means of wait state insertion. Refreshing must therefore
be performed by other means in these cases.
If a refresh request is generated internally while the external bus is released, the first request is
retained and a single refresh cycle will be executed after the bus-released state is cleared.
Figure 6.35 shows the bus cycle in this case.
When a bus cycle is extended by means of wait state insertion, the first request is retained in
the same way as when the external bus has been released.
In the event of contention with a bus request from an external bus master when a transition is
made to software standby mode, the BACK and strobe states may be indeterminate after the
transition to software standby mode (see figure 6.36).
Usage Notes
Figure 6.34 Example of Setup Procedure when Using DRAM Interface
Set bits CKS2 to CKS0 in RTMCSR
Wait for DRAM stabilization time
DRAM can be accessed
Set ABWCR
Set RTCOR
Set DRCRB
Set DRCRA