NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 109

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5
5.1
5.1.1
5.1.2
Table 38.
Intel
®
ICH8 Family Datasheet
Functional Description
This chapter describes the functions and interfaces of the ICH8 family.
PCI-to-PCI Bridge (D30:F0)
The PCI-to-PCI bridge resides in PCI Device 30, Function 0 on bus #0. This portion of
the ICH8 implements the buffering and control logic between PCI and Direct Media
Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI
decoder in this device must decode the ranges for the DMI. All register contents are
lost when core well power is removed.
Direct Media Interface (DMI) is the chip-to-chip connection between the Memory
Controller Hub / Graphics and Memory Controller Hub ((G)MCH) and I/O Controller Hub
8 (ICH8). This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
In order to provide for true isochronous transfers and configurable Quality of Service
(QoS) transactions, the ICH8 supports two virtual channels on DMI: VC0 and VC1.
These two channels provide a fixed arbitration scheme where VC1 is always the highest
priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (i.e., the ICH8 and
(G)MCH).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the Chipset Config Registers
(Section
PCI Bus Interface
The ICH8 PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.
The ICH8 integrates a PCI arbiter that supports up to four external PCI bus masters in
addition to the internal ICH8 requests.
PCI Bridge As an Initiator
The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge
generates the following cycle types:
PCI Bridge Initiator Cycle Types
I/O Read/Write
Memory Read/Write
Configuration Read/Write
Special Cycles
Command
7).
2h/3h
6h/7h
Ah/Bh
1h
C/BE#
Non-posted
Writes are posted
Non-posted
Posted
Notes
109