NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 507

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.2.3.2
Intel
®
ICH8 Family Datasheet
PxSCTL — Serial ATA Control Register (D31:F5)
Address Offset: BAR + 01h
Default Value:
This is a 32-bit read-write register by which software controls SATA capabilities. Writes
to the SControl register result in an action being taken by the ICH8 or the interface.
Reads from the register return the last value written to it.
31:20
19:16
15:12
11:8
7:4
3:0
Bit
Reserved
Port Multiplier Port (PMP) — RO. This field is not used by AHCI
NOTE: Port Multiplier not supported by ICH8.
Select Power Management (SPM) — RO. This field is not used by AHCI
Interface Power Management Transitions Allowed (IPM) — R/W. Indicates which
power states the ICH8 is allowed to transition to:
All other values reserved
Speed Allowed (SPD) — R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
All other values reserved.
ICH8 Supports Generation 1 communication rates (1.5 Gb/sec) and Gen 2 rates (3.0
Gb/s).
Device Detection Initialization (DET) — R/W. Controls the ICH8’s device detection
and interface initialization.
All other values reserved.
When this field is written to a 1h, the ICH8 initiates COMRESET and starts the
initialization process. When the initialization is complete, this field shall remain 1h until
set to another value by software.
This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field
while the ICH8 is running results in undefined behavior.
Value
Value
Value
0h
1h
2h
3h
0h
1h
2h
0h
1h
4h
00000004h
Description
No interface restrictions
Transitions to the PARTIAL state disabled
Transitions to the SLUMBER state disabled
Transitions to both PARTIAL and SLUMBER states disabled
Description
No speed negotiation restrictions
Limit speed negotiation to Generation 1 communication rate
Limit speed negotiation to Generation 2 communication rate
Description
No device detection or initialization action requested
Perform interface communication initialization sequence to
establish communication. This is functionally equivalent to a hard
reset and results in the interface being reset and communications
re-initialized
Disable the Serial ATA interface and put Phy in offline mode
Description
Attribute:
Size:
R/W, RO
32 bits
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