NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 630

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.1.13
16.1.14
16.1.15
630
INT_LN—Interrupt Line Register (SMBUS—D31:F3)
Address Offset: 3Ch
Default Value:
INT_PN—Interrupt Pin Register (SMBUS—D31:F3)
Address Offset: 3Dh
Default Value:
HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value:
7:0
Bit
7:0
Bit
7:4
Bit
3
2
1
0
Interrupt Line (INT_LN) — R/W. This data is not used by the ICH8. It is to
communicate to software the interrupt line that the interrupt pin is connected to
PIRQB#.
Interrupt PIN (INT_PN) — RO. This reflects the value of D31IP.SMIP in chipset
configuration space.
Reserved
Soft SMBUS Reset (SSRESET)— R/W.
0 = The HW will reset this bit to 0 when SMBus reset operation is completed.
1 = The SMBbus state machine and logic in ICH8 is reset.
I
0 = SMBus behavior.
1 = The ICH8 is enabled to communicate with I
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
1 = Enable. The SMB Host controller interface is enabled to execute commands. The
2
C_EN — R/W.
formatting of some commands.
to
This bit needs to be set for SMBALERT# to be enabled.
INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host
controller to interrupt or SMI#. Note that the SMB Host controller will not respond
to any new requests until all interrupt requests have been cleared.
Section 5.20.4
00h
See description
00h
(Interrupts / SMI#).
Description
Description
Description
Attributes:
Size:
Attributes:
Size:
Attribute:
Size:
2
C devices. This will change the
SMBus Controller Registers (D31:F3)
R/W
8 bits
RO
8 bits
R/W
8 bits
Intel
®
ICH8 Family Datasheet