NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 748

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 143.
20.1.1
748
Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)
BFPR—BIOS Flash Primary Region Register
(
Memory Address:SPIBAR + 00h
Default Value:
SPIBAR +
28:16
15:13
31:29
SPI Memory Mapped Configuration Registers
12:0
78h–7Bh
B0h–B3h
B4h–B7h
B8h–DFh
C1h–C4h
7Ch–7Fh
84h–87h
88h–8Fh
91h–93h
94h–95h
96h–97h
98h–9Fh
Bit
80–83h
Offset
90h
Reserved
BIOS Flash Primary Region Limit (PRL) — RO. This field specifies address
bits 24:12 for the Primary Region Limit.
The value in this register loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
Reserved
BIOS Flash Primary Region Base (PRB) — RO. This field specifies address
bits 24:12 for the Primary Region Base
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
Mnemonic
OPMENU
OPTYPE
PREOP
FDOD
FDOC
VSCC
SSFS
SSFC
FPR1
FPR2
FPR3
FPR4
—
—
00000000h
Opcode Menu Configuration
Flash Protected Range 3
Flash Protected Range 4
Reserved
Software Sequencing Flash Status
Software Sequencing Flash Control
Prefix Opcode Configuration
Opcode Type Configuration
Flash Descriptor Observability Control
Flash Descriptor Observability Data
Reserved
Vendor Specific Component Capabilities
Flash Protected Range 1
Flash Protected Range 2
Register Name
Description
Attribute:
Size:
)
Serial Peripheral Interface (SPI)
RO
32 bits
Intel
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000
Default
0000h
0000h
0000h
0000h
®
—
—
ICH8 Family Datasheet
RO, R/WC
RO, R/WL
Access
R/WL
R/WL
R/WL
R/WL
R/WL
R/W
R/W
R/W
R/W
RO
—
—