NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 769

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
20.2.4
20.2.4.1
20.2.4.2
Intel
®
ICH8 Family Datasheet
Flash Descriptor Master Section
FLMSTR1—Flash Master 1 (Host Processor/ BIOS)
Memory Address:FMBA + 000h
FLMSTR2—Flash Master 2 (ME)
Memory Address:FMBA + 004h
31:28
27
26
25
24
23:20
19
18
17
16
15:0
31:28
27
26
25
24
23:20
Bits
Bits
Reserved, must be zero
GbE Master Region Write Access: If the bit is set, this master can erase and write
that particular region through register accesses.
ME Master Region Write Access: If the bit is set, this master can erase and write
that particular region through register accesses.
Bit 26 is a don’t care as the primary master always has read/write permissions to it’s
primary region
Host CPU/BIOS Master Region Write Access: If the bit is set, this master can erase
and write that particular region through register accesses.
Flash Descriptor Master Region Write Access: If the bit is set, this master can
erase and write that particular region through register accesses.
Reserved, must be zero
Reserved, must be zero
GbE Master Region Write Access: If the bit is set, this master can erase and write
that particular region through register accesses.
ME Master Region Write Access: If the bit is set, this master can erase and write
that particular region through register accesses.
Host CPU/BIOS Master Region Write Access: If the bit is set, this master can erase
and write that particular region through register accesses.
Bit 25 is a don’t care as the primary master always has read/write permissions to it’s
primary region
Flash Descriptor Master Region Write Access: If the bit is set, this master can
erase and write that particular region through register accesses.
Reserved, must be zero
GbE Master Region Read Access: If the bit is set, this master can read that
particular region through register accesses.
ME Master Region Read Access: If the bit is set, this master can read that particular
region through register accesses.
Host CPU/BIOS Master Region Read Access: If the bit is set, this master can read
that particular region through register accesses.
Bit 17 is a don’t care as the primary master always has read/write permissions to it’s
primary region
Flash Descriptor Master Region Read Access: If the bit is set, this master can read
that particular region through register accesses.
Requester ID: This is the Requester ID of the Host CPU. This must be set to 0000h.
Description
Description
Size:
Size:
32 bits
32 bits
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