NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 251

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.26.4
Note:
5.27
Intel
®
ICH8 Family Datasheet
Power Button Sequence
When Intel Quick Resume Technology is enabled and the user presses the PWRBTN# to
indicate a desire to put the system into the Visual Off state, the following sequence is
assumed:
When PWRBTN_STS is set, the ICH8 causes an SCI and the normal OS handler for
PWRBTN_STS is called.
Feature Capability Mechanism
A new set of registers have been added into ICH8 LPC Interface (Device 31, Function 0,
offset E0h – EBh) that allows the system software or BIOS to easily determine the
features supported by ICH8. These registers can be accessed through LPC PCI
configuration space, thus allowing for convenient single point access mechanism for
chipset feature detection.
This set of registers consists of:
Capability ID (FDCAP)
Capability Length (FDLEN)
Capability Version and Vendor-Specific Capability ID (FDVER)
Feature Vector (FVECT)
1. User presses the Power Button, which causes the PWRBTN# signal to go low.
2. Intel Quick Resume Technology logic sets the EL_PB_STS bit. If the
3. Intel Quick Resume Technology logic causes an SMI or SCI (depending on the
4. If the Intel Quick Resume Technology logic was set to cause an SMI, the SMI
5. The Intel Quick Resume Technology SCI handler executes.
6. The Intel Quick Resume Technology SCI handler needs to cause the PWRBTN_STS
PWRBTN_INT_EN bit is set, the ICH8 does NOT set the PWRBTN_STS bit at this
point.
SMI_OPTION_CNT bit.)
handler executes and then sets the SCI_NOW_CNT bit.
bit to be set, it can do so by setting the PWRBTN_EVENT bit.
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