NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 583

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UHCI Controllers Registers
Intel
®
ICH8 Family Datasheet
15:13
5:4
Bit
12
11
10
9
8
7
6
3
Reserved — RO.
Suspend — R/W. This bit should not be written to a 1 if global suspend is active
(bit 3=1 in the USBCMD register). Bit 2 and bit 12 of this register define the hub states
as follows:
When in suspend state, downstream propagation of data is blocked on this port, except
for single-ended 0 resets (global reset and port reset). The blocking occurs at the end
of the current transaction, if a transaction was in progress when this bit was written to
1. In the suspend state, the port is sensitive to resume detection. Note that the bit
status does not change until the port is suspended and that there may be a delay in
suspending a port if there is a transaction currently in progress on the USB.
1 = Port in suspend state.
0 = Port not in suspend state.
NOTE: Normally, if a transaction is in progress when this bit is set, the port will be
Overcurrent Indicator — R/WC. Set by hardware.
0 = Software clears this bit by writing a 1 to it.
1 = Overcurrent pin has gone from inactive to active on this port.
Overcurrent Active — RO. This bit is set and cleared by hardware.
0 = Indicates that the overcurrent pin is inactive (high).
1 = Indicates that the overcurrent pin is active (low).
Port Reset — R/W.
0 = Port is not in Reset.
1 = Port is in Reset. When set, the port is disabled and sends the USB Reset signaling.
Low Speed Device Attached (LS) — RO.
0 = Full speed device is attached.
1 = Low speed device is attached to this port.
Reserved — RO. Always read as 1.
Resume Detect (RSM_DET) — R/W. Software sets this bit to a 1 to drive resume
signaling. The host controller sets this bit to a 1 if a J-to-K transition is detected for at
least 32 microseconds while the port is in the Suspend state. The ICH8 will then reflect
the K-state back onto the bus as long as the bit remains a 1, and the port is still in the
suspend state (bit 12,2 are ‘11’). Writing a 0 (from 1) causes the port to send a low
speed EOP. This bit will remain a 1 until the EOP has completed.
0 = No resume (K-state) detected/driven on port.
1 = Resume detected/driven on port.
Line Status — RO. These bits reflect the D+ (bit 4) and D– (bit 5) signals lines’ logical
levels. These bits are used for fault detect and recovery as well as for USB diagnostics.
This field is updated at EOF2 time (See Chapter 11 of the USB Specification).
Port Enable/Disable Change — R/WC. For the root hub, this bit gets set only when a
port is disabled due to disconnect on that port or due to the appropriate conditions
existing at the EOF2 point (See Chapter 11 of the USB Specification).
0 = No change. Software clears this bit by writing a 1 to the bit location.
1 = Port enabled/disabled status has changed.
Bits [12,2]
0, 1
1, 1
X,0
suspended when the current transaction completes. However, in the case of a
specific error condition (out transaction with babble), the ICH8 may issue a
start-of-frame, and then suspend the port.
Hub State
Suspend
Disable
Enable
Description
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