NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 194

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.15.3
5.15.3.1
194
Ultra ATA/100/66/33 Protocol
The ICH8 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for
a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to
33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and
Ultra ATA/100 can achieve read transfer rates up to 100 MB/s and write transfer rates
up to 88.9 MB/s.
The Ultra ATA/100/66/33 definition also incorporates a Cyclic Redundancy Checking
(CRC-16) error checking protocol.
Operation
Initial setup programming consists of enabling and performing the proper configuration
of the ICH8 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH8, this
consists of enabling synchronous DMA mode and setting up appropriate Synchronous
DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE
programming model is followed. Once programmed, the drive and ICH8 control the
transfer of data via the Ultra ATA/100/66/33 protocol. The actual data transfer consists
of three phases, a start-up phase, a data transfer phase, and a burst termination
phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to
begin the transfer, the ICH8 asserts DMACK# signal. When DMACK# signal is asserted,
the host controller drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the
ICH8 deasserts STOP, waits for the IDE device to assert DMARDY#, and then drives the
first data word and STROBE signal. For read cycles, the ICH8 tri-states the DD lines,
deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word
and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (ICH8
writes, IDE device
(latched by receiver) on each rising and falling edge of STROBE. The transmitter can
pause the burst by holding STROBE high or low, resuming the burst by again toggling
STROBE. The receiver can pause the burst by deasserting DMARDY# and resumes the
transfers by asserting DMARDY#. The ICH8 pauses a burst transaction to prevent an
internal line buffer over or under flow condition, resuming once the condition has
cleared. It may also pause a transaction if the current PRD byte count has expired,
resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst
termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data.
The ICH8 can stop a burst by asserting STOP, with the IDE device acknowledging by
deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the ICH8
acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a
high level. The ICH8 then drives the CRC value onto the DD lines and deassert
DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH8
terminates a burst transfer if it needs to service the opposite IDE channel, if a
Programmed I/O (PIO) cycle is executed to the IDE channel currently running the
burst, or upon transferring the last data from the final PRD.
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reads) providing data and toggling STROBE. Data is transferred
Intel
®
Functional Description
ICH8 Family Datasheet
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