NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 158

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.12.1.7
5.12.2
5.12.2.1
Table 61.
5.12.2.2
158
Deeper Sleep (DPSLP#) (Mobile Only)
This active-low signal controls the internal gating of the processor’s core clock. This
signal asserts before and deasserts after the STP_CPU# signal to effectively stop the
processor’s clock (internally) in the states in which STP_CPU# can be used to stop the
processor’s clock externally.
Dual-Processor Issues (Desktop Only)
Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently
than for uniprocessor designs.
DP Signal Differences
Power Management
For multiple-processor (or Multiple-core) configurations in which more than one Stop
Grant cycle may be generated, the (G)MCH is expected to count Stop Grant cycles and
only pass the last one through to the ICH8. This prevents the ICH8 from getting out of
sync with the processor on multiple STPCLK# assertions.
Because the S1 state will have the STPCLK# signal active, the STPCLK# signal can be
connected to both processors. However, for ACPI implementations, the BIOS must
indicate that the ICH8 only supports the C1 state for dual-processor designs.
In going to the S1 state for desktop, multiple Stop-Grant cycles will be generated by
the processors. The Intel ICH8 also has the option to assert the processor’s SLP# signal
(CPUSLP#). It is assumed that prior to setting the SLP_EN bit (which causes the
transition to the S1 state), the processors will not be executing code that is likely to
delay the Stop-Grant cycles.
In going to the S3, S4, or S5 states, the system will appear to pass through the S1
state; thus, STPCLK# and SLP# are also used. During the S3, S4, and S5 states, both
processors will lose power. Upon exit from those states, the processors will have their
power restored.
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Signal
Generally not used, but still supported by Intel
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both processors.
Generally not used, but still supported by ICH8.
Difference
®
ICH8.
Intel
®
Functional Description
ICH8 Family Datasheet