NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 771

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
20.2.5
20.2.5.1
Intel
®
ICH8 Family Datasheet
Flash Descriptor Strap
The following section of the Flash Descriptor is used to store strapping information.
The default value represents the internal strap signal value that is used if there is no
valid SPI Flash.
STRP0—Strap 0 Register
(Flash Descriptor Memory Mapped Configuration Registers)
Memory Address:FISBA + 000h
31:25
21:20
18:16
14:8
Bits
24
23
22
19
15
0000000b
0000000b
Default
00b
0
1
0
0
0
0
ME SmBus Addr[6:0] (ASD2): This field sets the 7-bit address for the
Intel AMT SMBus Controller 2.
Reserved
ME SmBus 2 Select (MESM2SEL):
0 =
1 = Management Engine SmBus Controller 2 is connected to the SmLink pins
SPI CS1# or LAN PHY Power Control (SPICS1_LANPHYPC_SEL)
0 = SPI_CS1# is used for SPI Chip Select
1 = SPI_CS1# is used for LAN PHY Power Control Function
NOTE: When configured as LAN PHY Power Control Function Bit 21=0 and
GPIO12 Select (GPIO12_SEL)
00 = GPIO12
01 = LAN PHY Power Control Function (Native Output)
11 = GLAN_DOCK# (Native Input)
10 = Invalid Configuration
NOTE: When configured for LAN PHY Power Control Function, Bit 22 of the
Integrated GbE or PCI Express Select (GLAN_PCIE_SEL):
0 = PCIe Port 6 is used for PCI Express
1 = PCIe Port 6 is used for integrated GLAN
NOTE: If the Gigabit Platform LAN Connected Device is not used, this bit
Reserved
BMC Mode (BMCMODE): This field is only valid when TCOMODE bit 7 is
set to 1.
0 = Not BMC mode. Supports Intel
1 = BMC Mode. Intel AMT SMBus Controller 1 is connected to SMLink.
ME SMBus Addr[6:0] (ASD): This field sets the 7-bit address for the Intel
AMT SMBus Controller 1.
Management Engine
ASF. Intel AMT SMBus Controller 1 is connected to SMBus.
Bit 20=1 of the Strap 0 register is an invalid configuration. The LAN
PHY Power Control Function configures the ICH8 signal used as an
output.
Strap 0 register must be set to 0. The LAN PHY Power Control
Function configures the ICH8 signal used as an output.
may be set to 0.
SmBus Controller 2 is connected to the SmBus pins
Size:
Description
®
Active Management Technology or
32 bits
771