NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 681

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Intel
17.2.20
17.2.21
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
CORBRP—CORB Read Pointer Register
(Intel
Memory Address:HDBAR + 4Ah
Default Value:
CORBCTL—CORB Control Register
(Intel
Memory Address:HDBAR + 4Ch
Default Value:
14:8
7:0
7:2
Bit
Bit
15
1
0
CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB
Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware
buffer within the High Definition Audio controller. The hardware will physically update
this bit to 1 when the CORB Pointer reset is complete. Software must read a 1 to verify
that the reset completed correctly. Software must clear this bit back to 0 and read back
the 0 to verify that the clear completed correctly. The CORB DMA engine must be
stopped prior to resetting the Read Pointer or else DMA transfer may be corrupted.
Reserved.
CORB Read Pointer (CORBRP)— RO. Software reads this field to determine how many
commands it can write to the CORB without over-running. The value read indicates the
CORB Read Pointer offset in DWord granularity. The offset entry read from this field has
been successfully fetched by the DMA controller and may be over-written by software;
supports 256 CORB entries (256 x 4B=1KB). This field may be read while the DMA
engine is running.
Reserved.
Enable CORB DMA Engine — R/W. After software writes a 0 to this bit, the hardware
may not stop immediately. The hardware will physically update the bit to 0 when the
DMA engine is truly stopped. Software must read a 0 from this bit to verify that the
DMA engine is truly stopped.
0 = DMA stop
1 = DMA run
CORB Memory Error Interrupt Enable — R/W.
0 = Disable
1 = Enable. The controller will generate an interrupt if the CMEI status bit (HDBAR +
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
4Dh: bit 0) is set.
0000h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
16 bits
R/W
8 bits
681