NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 192

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.15.2.2
5.15.2.3
Note:
5.15.2.4
192
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO
transfers. The DMA Timing Enable Only bits in IDE Timing register can be used to
program fast timing mode for DMA transactions only. This is useful for IDE devices
whose DMA transfer timings are faster than its PIO transfer timings. The IDE device
DMA request signal is sampled on the same PCI clock that DIOR# or DIOW# is
deasserted. If inactive, the DMA Acknowledge signal is deasserted on the next PCI
clock and no more transfers take place until DMA request is asserted again.
Interrupts
The ICH8 can generate interrupts based upon a signal coming from the PATA device, or
due to the completion of a PRD with the ‘I’ bit set. The interrupt is edge triggered and
active high. The PATA host controller generates IDEIRQ.
When the ICH8 IDE controller is operating independently from the SATA controller
(D31:F2), IDEIRQ will generate IRQ14. When operating in conjunction with the SATA
controller (combined mode), IDE interrupts will still generate IDEIRQ, but this may in
turn generate either IRQ14 or IRQ15, depending upon the value of the MAP.MV
(D31:F2:90h:bits 1:0) register. When in combined mode and the SATA controller is
emulating the logical secondary channel (MAP.MV = 1h), the PATA channel will emulate
the logical primary channel and IDEIRQ will generate IRQ14. Conversely, if the SATA
controller in combined mode is emulating the logical primary channel (MAP.MV=2h),
IDEIRQ will generate IRQ15.
IDE interrupts cannot be communicated through PCI devices or the serial IRQ stream.
Bus Master IDE Operation
To initiate a bus master transfer between memory and an IDE device, the following
steps are required:
1. Software prepares a PRD table in system memory. The PRD table must be dword-
2. Software provides the starting address of the PRD Table by loading the PRD Table
3. Software issues the appropriate DMA transfer command to the disk device.
4. The bus master function is engaged by software writing a 1 to the Start bit in the
5. Once the PRD is loaded internally, the IDE device will receive a DMA acknowledge.
6. The controller transfers data to/from memory responding to DMA requests from the
7. At the end of the transfer, the IDE device signals an interrupt.
8. In response to the interrupt, software resets the Start/Stop bit in the command
aligned and must not cross a 64-KB boundary.
Pointer Register. The direction of the data transfer is specified by setting the Read/
Write Control bit. The interrupt bit and Error bit in the Status register are cleared.
Command Register. The first entry in the PRD table is fetched and loaded into two
registers which are not visible by software, the Current Base and Current Count
registers. These registers hold the current value of the address and byte count
loaded from the PRD table. The value in these registers is only valid when there is
an active command to an IDE device.
IDE device. The IDE device and the host controller may or may not throttle the
transfer several times. When the last data transfer for a region has been completed
on the IDE interface, the next descriptor is fetched from the table. The descriptor
contents are loaded into the Current Base and Current Count registers.
register. It then reads the controller status followed by the drive status to
determine if the transfer completed successfully.
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Functional Description
ICH8 Family Datasheet