NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 654

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.1.24
17.1.25
654
PC—Power Management Capabilities Register
(Intel
Address Offset: 52h-53h
Default Value:
PCS—Power Management Control and Status Register
(Intel
Address Offset: 54h-57h
Default Value:
15:11
31:24
21:16
14:9
8:6
2:0
7:2
Bit
Bit
10
23
22
15
9
5
4
3
8
PME Support — RO. Hardwired to 11001b. Indicates PME# can be generated from D3
and D0 states.
D2 Support — RO. Hardwired to 0. Indicates that D2 state is not supported.
D1 Support —RO. Hardwired to 0. Indicates that D1 state is not supported.
Aux Current — RO. Hardwired to 001b. Reports 55 mA maximum suspend well current
required when in the D3
Device Specific Initialization (DSI) — RO. Hardwired to 0. Indicates that no device
specific initialization is required.
Reserved
PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.
Version — RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power
Management Specification.
Data — RO. Does not apply. Hardwired to 0.
Bus Power/Clock Control Enable — RO. Does not apply. Hardwired to 0.
B2/B3 Support — RO. Does not apply. Hardwired to 0.
Reserved.
PME Status (PMES) — R/WC.
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel
This bit is in the resume well and only cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
Reserved
PME Enable (PMEE) — R/W.
0 = Disable
1 = Enable. When set and if corresponding PMES also set, the Intel High Definition
This bit is in the resume well and only cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
Reserved
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
assert the PME# signal independent of the state of the PME_EN bit (bit 8 in this
register)
Audio controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE
+28h).
C842h
00000000h
COLD
state.
Intel
®
High Definition Audio controller would normally
®
Description
Description
High Definition Audio Controller Registers (D27:F0)
Attribute:
Size:
Attribute:
Size:
RO
16 bits
RO, R/W, R/WC
32 bits
Intel
®
ICH8 Family Datasheet