NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 438

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1.12
Note:
438
SECSTS—Secondary Status Register (PCI-PCI—D30:F0)
Offset Address: 1Eh
Default Value:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
10:9
4:0
Bit
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = Parity error not detected.
1 = Intel
Received System Error (RSE) — R/WC.
0 = SERR# assertion not received
1 = SERR# assertion is received on PCI.
Received Master Abort (RMA) — R/WC.
0 = No master abort.
1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the
Received Target Abort (RTA) — R/WC.
0 = No target abort.
1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is
Signaled Target Abort (STA) — R/WC.
0 = No target abort.
1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a
DEVSEL# Timing (DEVT) — RO.
01h = Medium decode timing.
Data Parity Error Detected (DPD) — R/WC.
0 = Conditions described below not met.
1 = The ICH8 sets this bit when all of the following three conditions are met:
Fast Back to Back Capable (FBC) — RO. Hardwired to 1 to indicate that the PCI to PCI
target logic is capable of receiving fast back-to-back cycles.
Reserved
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. This bridge is 33 MHz capable
only.
Reserved
• The bridge is the initiator on PCI.
• PERR# is detected asserted or a parity error is detected internally
• BCTRL.PERE (D30:F0:3E bit 0) is set.
cycle is master-aborted. For (G)MCH/ICH8 interface packets that have completion
required, this must also cause a target abort to be returned and sets PSTS.STA.
(D30:F0:06 bit 11)
target-aborted on PCI. For (G)MCH/ICH8 interface packets that have completion
required, this event must also cause a target abort to be returned, and sets
PSTS.STA. (D30:F0:06 bit 11).
target abort.
®
0280h
ICH8 PCI bridge detected an address or data parity error on the PCI bus
–
1Fh
Description
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
R/WC, RO
16 bits
Intel
®
ICH8 Family Datasheet