NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 610

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.2.2
Note:
610
USB2.0_STS—USB 2.0 Status Register
Offset:
Default Value:
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in section 4 of the EHCI specification for additional
information concerning USB 2.0 interrupt conditions.
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
31:16
11:6
Bit
15
14
13
12
5
Reserved. These bits are reserved and should be set to 0 when writing this register.
Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the
Asynchronous Schedule.
0 = Status of the Asynchronous Schedule is disabled. (Default)
1 = Status of the Asynchronous Schedule is enabled.
NOTE: The Host controller is not required to immediately disable or enable the
Periodic Schedule Status ⎯ RO. This bit reports the current real status of the Periodic
Schedule.
0 = Status of the Periodic Schedule is disabled. (Default)
1 = Status of the Periodic Schedule is enabled.
NOTE: The Host controller is not required to immediately disable or enable the Periodic
Reclamation ⎯ RO. 0=Default. This read-only status bit is used to detect an empty
asynchronous schedule. The operational model and valid transitions for this bit are
described in Section 4 of the EHCI Specification.
HCHalted ⎯ RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the
Reserved
Interrupt on Async Advance — R/WC. 0=Default. System software can force the host
controller to issue an interrupt the next time the host controller advances the
asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit
(D29:F7, D26:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit
indicates the assertion of that interrupt source.
Run/Stop bit being set to 0, either by software or by the Host controller hardware
(e.g., internal error). (Default)
Asynchronous Schedule when software transitions the Asynchronous Schedule
Enable bit (D29:F7, D26:F7:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD
register. When this bit and the Asynchronous Schedule Enable bit are the same
value, the Asynchronous Schedule is either enabled (1) or disabled (0).
Schedule when software transitions the Periodic Schedule Enable bit (D29:F7,
D26:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit and
the Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0).
MEM_BASE + 24h–27h
00001000h
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
R/WC, RO
32 bits
Intel
®
ICH8 Family Datasheet