NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 220

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.19.10
5.19.10.1
220
USB 2.0 Based Debug Port
The ICH8 supports the elimination of the legacy COM ports by providing the ability for
new debugger software to interact with devices on a USB 2.0 port.
High-level restrictions and features are:
The Debug port facilitates operating system and device driver debug. It allows the
software to communicate with an external console using a USB 2.0 connection.
Because the interface to this link does not go through the normal USB 2.0 stack, it
allows communication with the external console during cases where the operating
system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is
being debugged. Specific features of this implementation of a debug port are:
There are two operational modes for the USB debug port:
Behavioral Rules
Theory of Operation
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard
2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit
1. In both modes 1 and 2, the Debug Port controller must check for software
2. If the debug port is enabled by the debug driver, and the standard host controller
3. If the standard host controller driver suspends the USB port, then USB debug
4. The ENABLED_CNT bit in the debug register space is independent of the similar
• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.
• Works even though non-configured port is default-routed to the UHCI. Note that
• Allows normal system USB 2.0 traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be high-speed capable and connect directly to Port
• Debug Port FIFO always makes forward progress (a bad status on USB is simply
• The Debug Port FIFO is only given one USB access per microframe.
• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0
• Capability is interrupted when port is driving USB RESET
the Debug Port can not be used to debug an issue that requires a full-speed/low-
speed device on Port #0 using the UHCI drivers.
#0 on ICH8 systems (e.g., the DPD cannot be connected to Port #0 through a
hub).
presented back to software).
power state.
host controller driver. In Mode 1, the Debug Port controller is required to generate a
“keepalive” packets less than 2 ms apart to keep the attached debug device from
suspending. The keepalive packet should be a standalone 32-bit SYNC field.
is 1). In Mode 2, the normal transmission of SOF packets will keep the debug
device from suspending.
requested debug transactions at least every 125 microseconds.
driver resets the USB port, USB debug transactions are held off for the duration of
the reset and until after the first SOF is sent.
transactions are held off for the duration of the suspend/resume sequence and until
after the first SOF is sent.
port control bit in the associated Port Status and Control register.
Intel
®
Functional Description
ICH8 Family Datasheet