NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 157

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.12.1.3
Figure 10.
5.12.1.4
Table 60.
5.12.1.5
5.12.1.6
Intel
®
ICH8 Family Datasheet
FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric Error)
The ICH8 supports the coprocessor error function with the FERR#/IGNNE# pins. The
function is enabled via the COPROC_ERR_EN bit (Chipset Config Registers:Offset
31FFh:bit 1). FERR# is tied directly to the Coprocessor Error signal of the processor. If
FERR# is driven active by the processor, IRQ13 goes active (internally). When it
detects a write to the COPROC_ERR register (I/O Register F0h), the ICH8 negates the
internal IRQ13 and drives IGNNE# active. IGNNE# remains active until FERR# is driven
inactive. IGNNE# is never driven active unless FERR# is active.
Coprocessor Error Timing Diagram
If COPROC_ERR_EN is not set, the assertion of FERR# will not generate an internal
IRQ13, nor will the write to F0h generate IGNNE#.
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Table
NMI Sources
Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#)
The ICH8 power management logic controls these active-low signals. Refer to
Section 5.13
CPU Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. This signal represents a
logical AND of the ICH8’s PWROK and VRMPWRGD signals.
SERR# goes active (either internally,
externally via SERR# signal, or via
message from (G)MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
60.
I/O Write to F0h
Internal IRQ13
Cause of NMI
IGNNE#
for more information on the functionality of these signals.
FERR#
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
Can instead be routed to generate an SCI, through
the NMI2SCI_EN bit (Device 31:Function 0, TCO
Base + 08h, bit 11).
Comment
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