NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 482

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.1.27
f
12.1.28
482
PC—PCI Power Management Capabilities Register
(SATA–D31:F2)
Address Offset: 72h
Default Value:
PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)
Address Offset: 74h
Default Value:
15:11
14:9
Bits
Bits
7:4
1:0
8:6
2:0
15
10
8
3
2
9
5
4
3
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if this
bit and PMEE is set, a PME# will be generated from the SATA controller
Reserved
PME Enable (PMEE) — R/W. When set, the SATA controller generates PME# form
D3
Reserved
No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices
transitioning from D3
0 = Device transitioning from D3
1 = Device transitioning from D3
Configuration content is preserved. Upon transition from the D3
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the Power State bits.
Regardless of this bit, the controller transition from D3
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
Reserved
Power State (PS) — R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
11 = D3
When in the D3
memory spaces are not. Additionally, interrupts are blocked.
PME Support (PME_SUP) — RO. Indicates PME# can be generated from the D3
in the SATA host controller.
D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR) — RO. PME# from D3COLD state is not supported,
therefore this field is 000b.
Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-
specific initialization is required.
Reserved
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to
generate PME#.
Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI
Power Management Specification.
HOT
on a wake event.
HOT
4003h
0008h
state
–
–
HOT
73h
75h
state, the controller’s configuration space is available, but the I/O and
HOT
state to D0 state will perform an internal reset.
HOT
HOT
state to D0 state perform an internal reset.
state to D0 state do not perform an internal reset.
Description
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
HOT
state to D0 state by a system
RO
16 bits
RO, R/W, R/WC
16 bits
Intel
HOT
®
state to D0 state
ICH8 Family Datasheet
HOT
state