NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 261

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register and Memory Mapping
6.4
Table 102.
Intel
®
ICH8 Family Datasheet
Memory Map
Table 102
decodes. Cycles that arrive from DMI that are not directed to any of the internal
memory targets that decode directly from DMI will be driven out on PCI unless the
Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0).
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to DMI. Software must not attempt locks to the ICH8’s memory-
mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which
means potential deadlock conditions may occur.
Memory Decode Ranges from Processor Perspective (Sheet 1 of 2)
FED4 0000h–FED4 BFFFh
0000 0000h–000D FFFFh
FEC0 x000h–FEC0 x040h
FEC1 8000h–FEC1 8FFFh
FEC2 0000h–FEC2 7FFFh
FEC2 8000h–FEC2 8FFFh
FEC3 0000h–FEC3 7FFFh
FEC3 8000h–FEC3 8FFFh
000E 0000h–000E FFFFh
FFD0 0000h–FFD7 FFFFh
FFD8 0000h–FFDF FFFFh
000F 0000h–000F FFFFh
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
FF90 0000h–FF97 FFFFh
FF88 0000h–FF8F FFFFh
FF98 0000h–FF9F FFFFh
FFA0 0000h–FFA7 FFFFh
FEC1 0000h–FEC1 7FFF
FFE0 000h–FFE7 FFFFh
0010 0000h–TOM
Memory Range
(Top of Memory)
shows (from the processor perspective) the memory ranges that the ICH8
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
Firmware Hub (or PCI)
IO(x) APIC inside ICH8
PCI Express* Port 1
PCI Express* Port 2
PCI Express* Port 3
PCI Express* Port 4
PCI Express* Port 5
PCI Express* Port 6
Firmware Hub
Firmware Hub
Main Memory
TPM on LPC
Target
2
2
2
2
2
TOM registers in Host controller
Bit 6 in Firmware Hub Decode Enable
register is set
Bit 7 in Firmware Hub Decode Enable
register is set
X is controlled via APIC Range Select
(ASEL) field and APIC Enable (AEN) bit
PCI Express* Root Port 1 I/OxAPIC
Enable (PAE) set
PCI Express* Root Port 2 I/OxAPIC
Enable (PAE) set
PCI Express* Root Port 3 I/OxAPIC
Enable (PAE) set
PCI Express* Root Port 4 I/OxAPIC
Enable (PAE) set
PCI Express* Root Port 5 I/OxAPIC
Enable (PAE) set
PCI Express* Root Port 6 I/OxAPIC
Enable (PAE) set
Bit 8 in Firmware Hub Decode Enable
register is set
Bit 9 in Firmware Hub Decode Enable
register is set
Bit 10 in Firmware Hub Decode Enable
register is set
Bit 11 in Firmware Hub Decode Enable
register is set
Bit 12 in Firmware Hub Decode Enable
register is set
Dependency/Comments
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