NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 244

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.23.1.1
Figure 17.
244
Flash Descriptor
The maximum size of the Flash Descriptor is one 4KB block. The information stored in
the Flash Descriptor can only be written during the manufacturing process as its read/
write permissions must be set to Read only when the computer leaves the
manufacturing floor.
Flash Descriptor
The Flash signature as mentioned before is what selects Descriptor Mode as well as
verifying if the flash is programmed and functioning. The data at the bottom of the
flash (offset 0) must be 0FF0A55Ah in order to be in Descriptor mode. The Descriptor
map has pointers to the other six descriptor sections as well as the size of each. The
component section has information about the SPI flash in the system. It has number of
components, density of each, invalid instructions (such as chip erase), and frequencies
for read, fast read and write/erase instructions. The Region section points to the three
other regions as well as the size of each region. The master region contains the security
settings for the flash, granting read/write permissions for each region and identifying
each master. The MCH and ICH chipset soft strap sections contain MCH and ICH
configurable parameters. The Reserved for Chipset Future uses region between the top
of the MCH strap section and the bottom of the VSCC Table is reserved for future uses
or growth of the existing sections by the chipset. The Descriptor Upper Map is 256B
below the 4KB boundary of the descriptor. This determines the length and base address
of the VSCC Table. The VSCC Table holds the JEDEC ID and the VSCC information of all
the SPI Flash supported by that NVM image. The JEDEC and VSCC information is
necessary to allow devices that meet the compatibility requirements in
Section 5.23.2.2
is reserved at the top of the Flash Descriptor for use by OEM.
to work with Intel
The Flash Descriptor is broken up into six sections:
®
4KB
AMT, ASF, and/or Intel
0
Chipset future
Reserved for
VSCC Table
Upper MAP
Component
256B OEM
Descriptor
Descriptor
MCH Soft
Signature
ICH Soft
Section
Master
Region
Straps
Straps
uses
MAP
®
Quiet Technology. 256B
Intel
®
Functional Description
ICH8 Family Datasheet