NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 191

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.15.2
5.15.2.1
Figure 13.
Intel
®
ICH8 Family Datasheet
Bus Master Function
The ICH8 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master
channel is provided for the IDE connector. By performing the IDE data transfer as a PCI
Bus master, the ICH8 off-loads the processor and improves system performance in
multitasking environments. Both devices attached to the connector can be
programmed for bus master transfers, but only one device can be active at a time.
Physical Region Descriptor Format
The physical memory region to be transferred is described by a Physical Region
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.
The data transfer proceeds until all regions described by the PRDs in the table have
been transferred.
Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is
8 bytes in length. The first 4 bytes specify the byte address of a physical memory
region. This memory region must be dword-aligned and must not cross a 64-KB
boundary. The next two bytes specify the size or transfer count of the region in bytes
(64-KB limit per region). A value of 0 in these two bytes indicates 64-KB (thus the
minimum transfer count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this
is the final PRD in the Descriptor table. Bus master operation terminates when the last
descriptor has been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of
the Base Address is masked and byte enables are asserted for all read transfers. When
writing data, bit 1 of the Base Address is not masked and if set, will cause the lower
Word byte enables to be deasserted for the first dword transfer. The write to PCI
typically consists of a 32-byte cache line. If valid data ends prior to end of the cache
line, the byte enables will be deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to
or greater than the size of the disk transfer request. If greater than the disk transfer
request, the driver must terminate the bus master transaction (by setting bit 0 in the
Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal
transfer completion.
Physical Region Descriptor Table Entry
EOT
Byte 3
Memory Region Physical Base Address [31:1]
Reserved
Byte 2
Byte 1
Byte Count [15:1]
Byte 0
o
o
Main Memory
Memory
Region
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