NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 608

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.2.1
608
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
USB2.0_CMD—USB 2.0 Command Register
Offset:
Default Value:
31:24
23:16
• Suspend well hardware reset
• HCRESET
15:8
11:8
Bit
7
6
5
Reserved. These bits are reserved and should be set to 0 when writing this register.
Interrupt Threshold Control — R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Reserved. These bits are reserved and should be set to 0 when writing this register.
Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host
controller does not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0. The ICH8 does not implement this
optional reset.
Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by
software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is
Asynchronous Schedule Enable — R/W. Default 0b. This bit controls whether the
host controller skips processing the Asynchronous Schedule.
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Value
00h
01h
02h
04h
08h
10h
20h
40h
Advance status bit (D29:F7, D26:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS
register to a 1.
has evicted all appropriate cached schedule state, it sets the Interrupt on Async
Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance
Enable bit in the USB2.0_INTR register (D29:F7, D26:F7:CAPLENGTH + 28h, bit 5)
is a 1 then the host controller will assert an interrupt at the next interrupt
threshold. See the EHCI specification for operational details.
inactive. Doing so will yield undefined results.
MEM_BASE + 20–23h
00080000h
8 micro-frames (default, equates to 1 ms)
Maximum Interrupt Interval
16 micro-frames (2 ms)
32 micro-frames (4 ms)
64 micro-frames (8 ms)
2 micro-frames
4 micro-frames
1 micro-frame
Reserved
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7, D26:F7)
R/W, RO
32 bits
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ICH8 Family Datasheet