NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 238

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.21
5.21.1
5.21.1.1
238
Intel
The ICH8’s controller communicates with the external codec(s) over the Intel High
Definition Audio serial link. The controller consists of a set of DMA engines that are
used to move samples of digitally encoded data between system memory and an
external codec(s). The ICH8 implements four output DMA engines and 4 input DMA
engines. The output DMA engines move digital data from system memory to a D-A
converter in a codec. ICH8 implements a single Serial Data Output signal
(HDA_SDOUT) that is connected to all external codecs. The input DMA engines move
digital data from the A-D converter in the codec to system memory. The ICH8
implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four
codecs.
Audio software renders outbound and processes inbound data to/from buffers in
system memory. The location of individual buffers is described by a Buffer Descriptor
List (BDL) that is fetched and processed by the controller. The data in the buffers is
arranged in a predefined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bit/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the external codecs over the Intel High Definition Audio link. The input
DMA engines receive data from the codecs over the Intel High Definition Audio link and
format the data based on the programmable attributes for that stream. The data is
then written to memory in the predefined format for software to process. Each DMA
engine moves one stream of data. A single codec can accept or generate multiple
streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can
accept the same output stream processed by a single DMA engine.
Codec commands and responses are also transported to and from the codecs via DMA
engines.
Intel
Dock Sequence
Note that this sequence is followed when the system is running and a docking event
occurs.
1. Since the ICH8 supports docking, the Docking Supported (DCKSTS. DS) bit defaults
2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and
3. The physical docking event is signaled to ACPI BIOS software via ACPI control
4. ACPI BIOS software first checks that the docking is supported via DCKSTS.DS=1
5. The HD Audio controller then asserts the HDA_DOCK_EN# signal so that the BCLK
to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD
Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST
to effectively turn off the docking feature.
the Dock Mate (DCKSTS.DM) bit are both de-asserted. The HDA_DOCK_EN# signal
is de-asserted and HDA_DOCK_RST# is asserted. BCLK, SYNC and SDO signals
may or may no be running at the point in time that the docking event occurs.
methods. This is normally done through a GPIO signal on the ICH8 and is outside
the scope of this section of the specification.
and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1
to the DCKCTL.DA bit.
signal begins toggling to the dock codec. HDA_DOCK_EN# shall be asserted
synchronously to BCLK and timed such that BCLK is low, SYNC is low, and SDO is
low. Pull-down resistors on these signals in the docking station discharge the
signals low so that when the state of the signal on both sides of the switch is the
same when the switch is turned on. This reduces the potential for charge coupling
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High Definition Audio Docking (Mobile Only)
High Definition Audio Overview
Intel
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Functional Description
ICH8 Family Datasheet