NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 511

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NH82801HBM S LB9A

Manufacturer Part Number
NH82801HBM S LB9A
Description
CONTROLLER HUB, ICH8M, I/O, 82801HBM
Manufacturer
Intel
Datasheet

Specifications of NH82801HBM S LB9A

Power Dissipation Pd
2.4W
Digital Ic Case Style
BGA
No. Of Pins
676
Pci Bus Type
I/O Controller Hub
Pci Express Base Spec
PCIe 1.1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SATA Controller Registers (D31:F2)
12.3.2
Note:
Intel
®
ICH8 Family Datasheet
SDATA—SATA Index Data Register (D31:F5)
Address Offset: SIDPBA + 04h
Default Value:
These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and
SERR. The I/O space for these registers is allocated through SIDPBA.
31:0
Bit
Data (DATA)— R/W. This Data register is a “window” through which data is read or
written to the memory mapped registers. A read or write to this Data register triggers a
corresponding read or write to the memory mapped register pointed to by the Index
register. The Index register must be setup prior to the read or write to this Data
register.
Note that a physical register is not actually implemented as the data is actually stored
in the memory mapped registers.
Since this is not a physical register, the “default” value is the same as the default value
of the register pointed to by Index.
All bits undefined
Description
Attribute:
Size:
R/W
32 bits
511

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