NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 473

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.1.14
12.1.15
12.1.15.1
Intel
®
ICH8 Family Datasheet
BAR — Legacy Bus Master Base Address Register
(SATA–D31:F2)
Address Offset: 20h
Default Value:
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte IO space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA
Index Data Pair Base Address (SATA–D31:F2)
When the programming interface is not IDE (i.e., is not 01h), this register is named
ABAR. When the programming interface is IDE, this register becomes SIDPBA.
Note that hardware does not clear those BA bits when switching from IDE SKU to non-
IDE SKU or vice versa. BIOS is responsible for clearing those bits to 0 since the number
of writable bits changes after SKU switching (as indicated by a change in CC.SCC). In
the case, this register will then have to be re-programmed to a proper value.
When CC.SCC is not 01h
Address Offset: 24–27h
Default Value:
When the programming interface is not IDE, the register represents a memory BAR
allocating space for the AHCI memory registers defined in
NOTES:
1.
2.
31:16
31:11
15:4
10:4
3:1
2:1
Bit
Bit
0
3
0
When the MAP.MV register is programmed for combined mode (00b), this register is RO.
Software is responsible for clearing this bit before entering combined mode.
The ABAR register must be set to a value of 0001_0000h or greater.
Reserved
Base Address — R/W. This field provides the base address of the I/O space
(16 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Base Address (BA) — R/W. Base address of register memory space (aligned to 1 KB)
Reserved
Prefetchable (PF) — RO. Indicates that this range is not pre-fetchable
Type (TP) — RO. Indicates that this range can be mapped anywhere in 32-bit address
space.
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for register
memory space.
00000001h
00000000h
–
23h
Description
Description
Attribute:
Size:
Attribute:
Size:
Section
R/W, RO
32 bits
R/WO
32 bits
12.4.
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