NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 139

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.8
.
Table 50.
Note:
Intel
®
ICH8 Family Datasheet
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH8 incorporates the functionality of two 8259 interrupt controllers that provide
system interrupts for the ISA compatible interrupts. These interrupts are: system
timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE (Mobile only),
mouse, and DMA channels. In addition, this interrupt controller can support the PCI
based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line.
Each 8259 core supports eight interrupts, numbered 0–7.
cores are connected.
Interrupt Controller Core Connections
The ICH8 cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
ICH8 PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,
IRQ8#, and IRQ13.
Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH8. In the
following descriptions of the 8259s, the interrupt levels are in reference to the signals
at the internal interface of the 8259s, after the required inversions have occurred.
Therefore, the term “high” indicates “active,” which means “low” on an originating
PIRQ#.
Master
8259
Slave
Input
8259
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Internal
Keyboard
Internal
Serial Port A
Serial Port B
Parallel Port / Generic
Floppy Disk
Parallel Port / Generic
Internal Real Time
Clock
Generic
Generic
Generic
PS/2 Mouse
Internal
SATA,
IDE cable
(Mobile Only)
SATA,
IDE cable
(Mobile Only)
Typical Interrupt
Source
Internal Timer / Counter 0 output / HPET #0
IRQ1 via SERIRQ
Slave controller INTR output
IRQ3 via SERIRQ, PIRQ#
IRQ4 via SERIRQ, PIRQ#
IRQ5 via SERIRQ, PIRQ#
IRQ6 via SERIRQ, PIRQ#
IRQ7 via SERIRQ, PIRQ#
Internal RTC / HPET #1
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
SATA Primary (legacy mode), or SERIRQ, or
PIRQ#.
Mobile Only: IDEIRQ (legacy mode, non-combined
or combined mapped as primary).
SATA Secondary (legacy mode), or SERIRQ, or
PIRQ#.
Mobile Only: IDEIRQ (legacy mode — combined,
mapped as secondary).
Connected Pin / Function
Table 50
shows how the
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