NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 616

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.2.2.9
616
PORTSC—Port N Status and Control Register
Offset:
Attribute:
Default Value:
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the EHCI specification for operational requirements for how change events interact with
port suspend mode.
31:23
• No device connected
• Port disabled.
Bit
22
21
20
Reserved. These bits are reserved for future use and will return a value of 0’s when
read.
Wake on Overcurrent Enable (WKOC_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Disconnect Enable (WKDSCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Connect Enable (WKCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the overcurrent
Active bit (bit 4 of this register) is set.
Management Control/Status Register (offset 54, bit 15) when the Current Connect
Status changes from connected to disconnected (i.e., bit 0 of this register changes
from 1 to 0).
Management Control/Status Register (offset 54, bit 15) when the Current Connect
Status changes from disconnected to connected (i.e., bit 0 of this register changes
from 0 to 1).
Port 0, Port 6: MEM_BASE + 64h
Port 1, Port 7: MEM_BASE + 68
Port 2, Port 8: MEM_BASE + 6C
Port 3, Port 9: MEM_BASE + 70
Port 4: MEM_BASE + 74
Port 5: MEM_BASE + 78
R/W, R/WC, RO
00003000h
Description
–
–
77h (Device 29 Only)
7Bh (Device 29 Only)
Size:
–
–
EHCI Controller Registers (D29:F7, D26:F7)
–
6Bh
6Fh
73h
–
67h
32 bits
Intel
®
ICH8 Family Datasheet