NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 617

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
Intel
®
ICH8 Family Datasheet
19:16
15:14
11:10
Bit
13
12
9
Port Test Control — R/W. When this field is 0s, the port is NOT operating in a test
mode. A non-zero value indicates that it is operating in test mode and the specific test
mode is indicated by the specific value. The encoding of the test mode bits are (0110b
– 1111b are reserved):
Refer to USB Specification Revision 2.0, Chapter 7 for details on each test mode.
Reserved — R/W. Should be written to =00b.
Port Owner — R/W. Default = 1b. This bit unconditionally goes to a 0 when the
Configured Flag bit in the USB2.0_CMD register makes a 0 to 1 transition.
System software uses this field to release ownership of the port to a selected host
controller (in the event that the attached device is not a high-speed device). Software
writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit
means that a companion host controller owns and controls the port. See Section 4 of
the EHCI Specification for operational details.
Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does
have power.
Line Status— RO.These bits reflect the current logical levels of the D+ (bit 11) and D–
(bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to
the port reset and enable sequence. This field is valid only when the port enable bit is 0
and the current connect status bit is set to a 1.
00 = SE0
10 = J-state
01 = K-state
11 = Undefined
Reserved. This bit will return a 0 when read.
Value
0000b
0001b
0010b
0011b
0100b
0101b
Test mode not enabled (default)
Maximum Interrupt Interval
FORCE_ENABLE
Test SE0_NAK
Test K_STATE
Test J_STATE
Test Packet
Description
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