NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 358

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.3
9.4.4
358
ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller
Default Value:
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0)
Offset Address: 21h
Default Value:
7:3
2:0
7:3
1:0
Bit
Bit
2
Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the
interrupt vector table for the interrupt routines associated with each interrupt request
level input.
Interrupt Request Level — WO. When writing ICW2, these bits should all be 0.
During an interrupt acknowledge cycle, these bits are programmed by the interrupt
controller with the interrupt to be serviced. This is combined with bits [7:3] to form the
interrupt vector driven onto the data bus during the second INTA# cycle. The code is a
three bit binary code:
0 = These bits must be programmed to 0.
Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the
slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through
the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2.
IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR
signal is asserted to the processor, and the returning interrupt acknowledge returns the
interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
0 = These bits must be programmed to 0.
Code
000b
001b
010b
011b
100b
101b
110b
111b
Slave Controller
All bits undefined
All bits undefined
Master Interrupt
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
–
–
A1h
21h
Slave Interrupt
Description
Description
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Attribute:
Size:
Attribute:
Size:
IRQ8
IRQ9
LPC Interface Bridge Registers (D31:F0)
WO
8 bit /controller
WO
8 bits
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ICH8 Family Datasheet