NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 744

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.1.4
.
19.1.5
Note:
744
MAIN_CNT—Main Counter Value Register
Address Offset: 0F0h
Default Value:
TIMn_CONF—Timer n Configuration and Capabilities
Register
Address Offset: Timer 0:
Default Value:
The letter n can be 0, 1, or 2, referring to Timer 0, 1 or 2.
55:52,
51:44,
63:56
42:14
63:0
13:9
Bit
Bit
43
Reserved. These bits will return 0 when read.
Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) — RO.
Timer 0, 1:Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and
23) have a value of 1. Writes will have no effect.
Timer 2:Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22,
and 23) have a value of 1. Writes will have no effect.
NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared
Reserved. These bits return 0 when read.
Interrupt Rout (TIMERn_INT_ROUT_CNF) — R/W. This 5-bit field indicates the
routing for the interrupt to the I/O (x) APIC. Software writes to this field to select
which interrupt in the I/O (x) will be used for this timer’s interrupt. If the value is not
supported by this particular timer, then the value read back will not match what is
written. The software must only write valid values.
NOTES:
1.
2.
3.
Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of
the counter. Writes load the new value to the counter.
NOTES:
1.
2.
3.
4.
5.
with any other devices to assure the proper operation of HPET #2.
different routing, and this bit field has no effect for those two timers.
Timer 0,1: Software is responsible to make sure it programs a valid value (20,
21, 22, or 23) for this field. The ICH8 logic does not check the validity of the
value written.
Timer 2: Software is responsible to make sure it programs a valid value (11,
20, 21, 22, or 23) for this field. The ICH8 logic does not check the validity of
the value written.
counter. Since this delays the interrupts for all of the timers, this should be
done only if the consequences are understood. It is strongly recommended
that 32-bit software only operate the timer in 32-bit mode.
Reads to this register are monotonic. No two consecutive reads return the
same value. The second of two reads always returns a larger value (unless
the timer has rolled over to 0).
N/A
Timer 1:
Timer 2:
N/A
If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a
Writes to this register should only be done while the counter is halted.
Reads to this register return the current value of the main counter.
32-bit counters will always return 0 for the upper 32-bits of this register.
If 32-bit software attempts to read a 64-bit counter, it should first halt the
100–107h,
120–127h,
140–147h
Description
Description
Attribute:
Size:
Attribute:
Size:
High Precision Event Timer Registers
R/W
64 bits
RO, R/W
64 bits
Intel
®
ICH8 Family Datasheet