NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 284

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.43
7.1.44
7.1.45
284
CIR5—Chipset Initialization Register 5
Offset Address: 1D40h–1D47h
Default Value:
TRSR—Trap Status Register
Offset Address: 1E00–1E03h
Default Value:
TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h
Default Value:
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
63:25
23:20
19:16
63:1
31:4
15:2
3:0
1:0
Bit
Bit
Bit
24
0
Reserved
CIR5 Field 1 — R/W. BIOS must program this field to 1b
Reserved
Cycle Trap SMI# Status (CTSS) — R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and
trapped). These bits are OR’ed together to create a single status bit in the Power
Management register space.
Note that the SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby
assuring that the processor can enter the SMI# handler when the instruction
completes. Each status bit is cleared by writing a 1 to the corresponding bit location
in this register.
Reserved
Read/Write# (RWI) — RO.
0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
Reserved
Active-high Byte Enables (AHBE) — RO. This is the dword-aligned byte enables
associated with the trapped cycle. A 1 in any bit location indicates that the
corresponding byte is enabled in the cycle.
Trapped I/O Address (TIOA) — RO. This is the dword-aligned address of the
trapped cycle.
Reserved
0000000000000000h
00000000h
0000000000000000h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
R/W, R/WL
64-bit
R/WC, RO
32-bit
RO
64-bit
Intel
®
ICH8 Family Datasheet