NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 113

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.1.8
Warning:
5.2
5.2.1
Table 40.
Intel
®
ICH8 Family Datasheet
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus
cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration
space is supported by a mapping mechanism implemented within the ICH8. The PCI
Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration
space, Mechanism 1 and Mechanism 2. The ICH8 only supports Mechanism 1.
Configuration writes to internal devices, when the devices are disabled, are invalid and
may cause undefined results.
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)
There are six root ports available in ICH8. These all reside in device 28, and take
function 0 – 5. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is
function 3, port 5 is function 4, and port 6 is function 5.
Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated via the legacy pin, the pin is internally routed to the
ICH8 interrupt controllers. The pin that is driven is based upon the setting of the
chipset configuration registers. Specifically, the chipset configuration registers used are
the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Table 40
refers to the Hot-Plug and PME interrupt bits.
MSI vs. PCI IRQ Actions
All bits 0
One or more bits set to 1
One or more bits set to 1, new bit gets set to 1
One or more bits set to 1, software clears some (but not all)
bits
One or more bits set to 1, software clears all bits
Software clears one or more bits, and one or more bits are
set on the same clock
summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
Interrupt Register
Wire inactive
Wire active
Wire inactive
Wire active
Wire active
Wire active
Wire-Mode
Action
No action
Send
message
Send
message
Send
message
No action
Send
message
MSI Action
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