NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 381

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.1.3
Intel
®
ICH8 Family Datasheet
NOTE: VRMPWROK is sampled using the RTC clock. Therefore, low times that are less than one
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4h
Default Value:
Lockable:
15:9
7:6
Bit
8
Bit
2
1
0
RTC clock period may not be detected by the ICH8.
Reserved
S4_STATE# Pin Disable — R/W.
0 = The traditional SLP_S4# signal (without ME Overrides) is driven on the S4_STATE#
1 = The S4_STATE# pin functionality is disabled and the pin can be used for other
This bit is cleared by RTCRST#.
SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.
Valid values are:
00 = 1.5 ms ± 0.6 ms
01 = 16 ms ± 4 ms
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
Minimum SLP_S4# Assertion Width Violation Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some
CPU Power Failure (CPUPWR_FLR) — R/W.
0 = Software (typically BIOS) clears this bit by writing a 0 to it.
1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while
NOTE: VRMPWRGD is sampled using the RTC clock. Therefore, low times that are
PWROK Failure (PWROK_FLR) — R/WC.
0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3
1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1
NOTE: See
NOTE: In the case of true PWROK failure, PWROK will go low first before the
Pin.
functionality.
programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset
A4h:bits 5:4). The ICH8 begins the timer when SLP_S4# is asserted during S4/
S5 entry, or when the RSMRST# input is deasserted during G3 exit. Note that
this bit is functional regardless of the value in the SLP_S4# Assertion Stretch
Enable (D31:F0:Offset A4h:bit 3).
the system was in an S0 or S1 state.
state.
state. The bit will be cleared only by software by writing a 1 to this bit or when
the system goes to a G3 state.
00h
No
cases before the default value is readable.
less than one RTC clock period may not be detected by the Intel ICH8.
VRMPWRGD.
Chapter 5.13.11.3
for more details about the PWROK pin functionality.
Description
Description
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
16-bit
ACPI, Legacy
RTC
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