NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 131

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.5.3
5.5.3.1
Table 47.
Note:
Table 48.
5.5.4
Intel
®
ICH8 Family Datasheet
Summary of DMA Transfer Sizes
Table 47
Word Count Register” indicates that the register contents represents either the number
of bytes to transfer or the number of 16-bit words to transfer. The column labeled
“Current Address Increment/Decrement” indicates the number added to or taken from
the Current Address register after each DMA transfer cycle. The DMA Channel Mode
Register determines if the Current Address Register will be incremented or
decremented.
Address Shifting When Programmed for 16-Bit I/O Count by Words
DMA Transfer Size
The ICH8 maintains compatibility with the implementation of the DMA in the PC AT that
used the 82C37. The DMA shifts the addresses for transfers to/from a 16-bit device
count-by-words.
The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
When programming the Current Address Register (when the DMA channel is in this
mode), the Current Address must be programmed to an even address with the address
value shifted right by one bit.
The address shifting is shown in
Address Shifting in 16-Bit I/O DMA Transfers
NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following TC. The Base Registers are loaded simultaneously
with the Current Registers by the microprocessor when the DMA channel is
programmed and remain unchanged throughout the DMA service. The mask bit is not
set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ
is detected.
8-Bit I/O, Count By Bytes
16-Bit I/O, Count By Words (Address
Shifted)
DMA Device Date Size And Word Count
lists each of the DMA device transfer sizes. The column labeled “Current Byte/
A[23:17]
Address
Output
A[16:1]
A0
8-Bit I/O Programmed
Table
Address (Ch 0–3)
48.
A[23:17]
A[16:1]
A0
Current Byte/Word
Count Register
Words
Bytes
16-Bit I/O Programmed
Address (Ch 5–7)
Current Address
(Shifted)
A[23:17]
A[15:0]
Increment/
Decrement
0
1
1
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