NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 529

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller Registers (D31:F2)
12.4.2.7
Intel
®
ICH8 Family Datasheet
PxCMD—Port [5:0] Command Register (D31:F2)
Address Offset: Port 0: ABAR + 118h
Default Value:
31:28
Bit
27
26
25
Interface Communication Control (ICC) — R/W. This is a four bit field which
can be used to control reset and power states of the interface. Writes to this field
will cause actions on the interface, either as primitives or an OOB sequence, and
the resulting status of the interface will be reported in the PxSSTS register
(Address offset Port 0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h,
Port 3: ABAR+2A4h, Port 4: ABAR+224h, Port 5: ABAR+2A4h).
When system software writes a non-reserved value other than No-Op (0h), the
ICH8 will perform the action and update this field back to Idle (0h).
If software writes to this field to change the state to a state the link is already in
(e.g. interface is in the active state and a request is made to go to the active
state), the ICH8 will take no action and return this field to Idle.
NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to
Aggressive Slumber / Partial (ASP) — R/W. When set, and the ALPE bit (bit
26) is set, the ICH8 shall aggressively enter the slumber state when it clears the
PxCI register and the PxSACT register is cleared. When cleared, and the ALPE bit is
set, the ICH8 will aggressively enter the partial state when it clears the PxCI
register and the PxSACT register is cleared. If CAP.SALP is cleared to '0', software
shall treat this bit as reserved.
Aggressive Link Power Management Enable (ALPE) — R/W. When set, the
ICH8 will aggressively enter a lower link power state (partial or slumber) based
upon the setting of the ASP bit (bit 27).
Drive LED on ATAPI Enable (DLAE) — R/W. When set, the ICH8 will drive the
LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA
commands. When cleared, the ICH8 will only drive the LED pin active for ATA
commands. See
Value
Fh–7h
5h–3h
Port 1: ABAR + 198h
Port 2: ABAR + 218h
Port 3: ABAR + 298h (Desktop Only)
Port 4: ABAR + 318h (Desktop Only)
Port 5: ABAR + 398h (Desktop Only)
0000w00wh
where w = 00?0b (for?, see bit description)
6h
2h
1h
0h
02h or 06h.
Definition
Reserved
Slumber: This will cause the Intel
the interface to the slumber state. The SATA device may reject
the request and the interface will remain in its current state
Reserved
Partial: This will cause the ICH8 to request a transition of the
interface to the partial state. The SATA device may reject the
request and the interface will remain in its current state.
Active: This will cause the ICH8 to request a transition of the
interface into the active
No-Op / Idle: When software reads this value, it indicates the
ICH8 is not in the process of changing the interface state or
sending a device reset, and a new link command may be issued.
Section 5.16.5
for details on the activity LED.
Description
Attribute:
Size:
®
ICH8 to request a transition of
R/W, RO, R/WO
32 bits
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