NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 403

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
Intel
®
ICH8 Family Datasheet
(ICH8DH
ICH8DO
(Mobile
ICH8R,
(ICH8
Base,
Only)
Only)
Only)
Bit
11
10
10
10
9
8
PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the
Reserved
QRT_SCI_STS — R/WC: In Desktop Mode, when Quick Resume Technology
feature is enabled, this bit will be set by hardware when the SCI_NOW_CNT or
QRT_PB_SCI_STS bit goes high. Software clears the bit by writing a 1 to the bit
position.
In Desktop Mode, when QRT feature is disabled, this bit will be treated as
Reserved.
BATLOW_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = BATLOW# Not asserted
1 = Set by hardware when the BATLOW# signal is asserted.
PCI_EXP_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
NOTES:
1.
2.
3.
4.
RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
• The PME event message was received on one or more of the PCI Express* ports
• An Assert PMEGPE message received from the (G)MCH via DMI
PME_EN bit is set, and the system is in an S0 state, then the setting of the
PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the
PME_EN bit is set, and the system is in an S1–S4 state (or S5 state due to
setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will
generate a wake event, and an SCI will be generated. If the system is in an S5
state due to power button override or a power failure, then PME_STS will not
cause a wake event or SCI.
The PCI WAKE# pin has no impact on this bit.
If the PCI_EXP_STS bit went active due to an Assert PMEGPE message,
then a Deassert PMEGPE message must be received prior to the software
write in order for the bit to be cleared.
If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the
level-triggered SCI will remain active.
A race condition exists where the PCI Express device sends another PME
message because the PCI Express device was not serviced within the time
when it must resend the message. This may result in a spurious interrupt,
and this is comprehended and approved by the PCI Express* Specification,
Revision 1.0a. The window for this race condition is approximately 95-105
milliseconds.
Description
403