NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 271

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chipset Configuration Registers
7.1.9
7.1.10
Intel
®
ICH8 Family Datasheet
V1CAP—Virtual Channel 1 Resource Capability Register
Offset Address: 001C–001Fh
Default Value:
V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 0020–0023h
Default Value:
31:24
22:16
30:27
26:24
23:20
19:17
13:8
15:8
7:0
7:1
Bit
Bit
23
15
14
31
16
0
Port Arbitration Table Offset (AT) — RO. Indicates the location of the port arbitration
table in the root complex. A value of 3h indicates the table is at offset 30h.
Reserved
Maximum Time Slots (MTS) — R/WO. This value is updated by platform BIOS
based upon the determination of the number of time slots available in the platform.
Reject Snoop Transactions (RTS) — RO. All snoopable transactions on VC1 are
rejected. This VC is for isochronous transfers only.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not
just advanced packet switching transactions.
Reserved
Port Arbitration Capability (PAC) — RO. Indicates the port arbitration capability is
time-based WRR of 128 phases.
Virtual Channel Enable (EN) — R/W. Enables the VC when set. Disables the VC
when cleared.
Reserved
Virtual Channel Identifier (ID) — R/W. Indicates the ID to use for this virtual
channel.
Reserved
Port Arbitration Select (PAS) — R/W. Indicates which port table is being
programmed. The only permissible value of this field is 4h for the time-based WRR
entries.
Load Port Arbitration Table (LAT) — RO/W. When set, the port arbitration table
loaded based upon the PAS field in this register. This bit always returns 0 when read.
Reserved
Transaction Class / Virtual Channel Map (TVM) — R/W. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
Reserved
30008010h
00000000h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/WO, RO
32-bit
R/W, RO
32-bit
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