NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 684

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2.27
17.2.28
684
RINTCNT—Response Interrupt Count Register
(Intel
Memory Address:HDBAR + 5Ah
Default Value:
RIRBCTL—RIRB Control Register
(Intel
Memory Address:HDBAR + 5Ch
Default Value:
15:8
31:0
7:3
Bit
Bit
2
1
0
Reserved.
N Response Interrupt Count — R/W.
0000 0001b = 1 response sent to RIRB
...........
1111 1111b = 255 responses sent to RIRB
0000 0000b = 256 responses sent to RIRB
The DMA engine should be stopped when changing this field; otherwise, an interrupt
may be lost.
Note that each response occupies 2 DWords in the RIRB.
This is compared to the total number of responses that have been returned, as opposed
to the number of frames in which there were responses. If more than one codecs
responds in one frame, then the count is increased by the number of responses
received in the frame.
Reserved.
Response Overrun Interrupt Control — R/W. If this bit is set, the hardware will
generate an interrupt when the Response Overrun Interrupt Status bit (HDBAR + 5Dh:
bit 2) is set.
Enable RIRB DMA Engine — R/W. After software writes a 0 to this bit, the hardware
may not stop immediately. The hardware will physically update the bit to 0 when the
DMA engine is truly stopped. Software must read a 0 from this bit to verify that the
DMA engine is truly stopped.
0 = DMA stop
1 = DMA run
Response Interrupt Control — R/W.
0 = Disable Interrupt
1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
when an empty Response slot is encountered on all SDI[x] inputs (whichever
occurs first). The N counter is reset when the interrupt is generated.
0000h
00h
Intel
®
Description
Description
High Definition Audio Controller Registers (D27:F0)
Attribute:
Size:
Size:
Attribute:
R/W
16 bits
R/W
8 bits
Intel
®
ICH8 Family Datasheet