NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 164

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 65.
164
Causes of SMI# and SCI (Sheet 2 of 2)
NOTES:
1.
2.
3.
4.
5.
6.
7.
TCO SMI — Write attempted
to BIOS
BIOS_RLS written to
GBL_RLS written to
Write to B2h register
Periodic timer expires
64 ms timer expires
Enhanced USB Legacy
Support Event
Enhanced USB Intel Specific
Event
UHCI USB Legacy logic
Serial IRQ SMI reported
Device monitors match
address in its range
SMBus Host Controller
SMBus Slave SMI message
SMBus SMBALERT# signal
active
SMBus Host Notify message
received
(Mobile Only) BATLOW#
assertion
Access microcontroller 62h/
66h
SLP_EN bit written to 1
USB Per-Port Registers Write
Enable bit changes to 1.
SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
GBL_SMI_EN must be 1 to enable SMI.
ICH8 must have SMI# fully enabled when ICH8 is also enabled to trap cycles. If SMI# is
Only GPI[15:0] may generate an SMI# or SCI.
When a power button override first occurs, the system will transition immediately to S5.
The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)
is not cleared prior to setting SCI_EN.
SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
EOS must be written to 1 to re-enable SMI for the next 1.
not enabled in conjunction with the trap enabling, then hardware behavior is undefined.
Cause
No
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
No
No
No
SCI
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SMI
BIOSWP=1
GBL_EN=1
BIOS_EN=1
APMC_EN = 1
PERIODIC_EN=1
SWSMI_TMR_EN=1
LEGACY_USB2_EN = 1 LEGACY_USB2_STS
INTEL_USB2_EN = 1
LEGACY_USB_EN=1
none
none
SMB_SMI_EN
Host Controller
Enabled
none
none
HOST_NOTIFY_INTRE
N
BATLOW_EN=1.
MCSMI_EN
SMI_ON_SLP_EN=1
USB2_EN=1,
Write_Enable_SMI_En
able=1
Additional Enables
Intel
SERIRQ_SMI_STS
BIOSWR_STS
GBL_STS
BIOS_STS
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
INTEL_USB2_STS
LEGACY_USB_STS
DEVMON_STS,
DEVACT_STS
SMBus host status
reg.
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBUS_SMI_STS
HOST_NOTIFY_STS
BATLOW_STS
MCSMI_STS
SMI_ON_SLP_EN_STS
USB2_STS, Write
Enable Status
®
Functional Description
Where Reported
ICH8 Family Datasheet