NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 609

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EHCI Controller Registers (D29:F7, D26:F7)
Intel
®
ICH8 Family Datasheet
NOTE: The Command Register indicates the command to be executed by the serial bus host
3:2
Bit
4
1
0
controller. Writing to the register causes a command to be executed.
Periodic Schedule Enable — R/W. Default 0b. This bit controls whether the host
controller skips processing the Periodic Schedule.
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
Frame List Size — RO. The ICH8 hardwires this field to 00b because it only supports
the
1024-element frame list size.
Host Controller Reset (HCRESET) — R/W. This control bit used by software to reset
the host controller. The effects of this on root hub registers are similar to a Chip
Hardware Reset
(i.e., RSMRST# assertion and PWROK deassertion on the ICH8).
When software writes a 1 to this bit, the host controller resets its internal pipelines,
timers, counters, state machines, etc. to their initial value. Any transaction currently in
progress on USB is immediately terminated. A USB reset is not driven on downstream
ports.
NOTE: PCI configuration registers and Host controller capability registers are not
All operational registers, including port registers and port state machines are set to
their initial values. Port ownership reverts to the companion host controller(s), with the
side effects described in the EHCI spec. Software must re-initialize the host controller in
order to return the host controller to an operational state.
This bit is set to 0 by the host controller when the reset process is complete. Software
cannot terminate the reset process early by writing a 0 to this register.
Software should not set this bit to a 1 when the HCHalted bit (D29:F7,
D26:F7:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to
reset an actively running host controller will result in undefined behavior. This reset me
be used to leave EHCI port test modes.
Run/Stop (RS) — R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.
Software should not write a 1 to this field unless the host controller is in the Halted
state (i.e., HCHalted in the USBSTS register is a 1). The Halted bit is cleared
immediately when the Run bit is set.
The following table explains how the different combinations of Run and Halted should
be interpreted:
Memory read cycles initiated by the EHC that receive any status other than Successful
will result in this bit being cleared.
Run/Stop
The Host controller continues execution as long as this bit is set. When this bit is
set to 0, the Host controller completes the current transaction on the USB and then
halts. The HCHalted bit in the USB2.0_STS register indicates when the Host
controller has finished the transaction and has entered the stopped state.
0b
0b
1b
1b
effected by this reset.
Halted
0b
1b
0b
1b
Interpretation
In the process of halting
Halted
Running
Invalid - the HCHalted bit clears immediately
Description
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