NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 387

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LPC Interface Bridge Registers (D31:F0)
9.8.1.8
9.8.1.9
Intel
®
ICH8 Family Datasheet
PMIR—Power Management Initialization Register
Offset Address: ACh
Default Value:
QRT_STS (PM—D31:F0): Quick Resume Technology Status Register
(Intel
Offset Address: B0h
Default Value:
Lockable:
Power Well:
31:21
19:0
Bit
7:5
Bit
20
4
3
2
1
0
®
Reserved
CF9h Global Reset (CF9GR) — R/W. When set, a CF9h write of 6h or Eh will cause a
Global Reset of both the Host and the ME partitions. If this bit is cleared, a CF9h write
of 6h or Eh will only reset the Host partition.
Reserved
Reserved
QRT_SCI_NOW_STS— R/WC: This bit goes active when software writes a ‘1’ to
QRT_CNT1.SCI_NOW_CNT. It can be enabled to cause an SCI which will allow the QRT
software to transition the reaction to an QRT event from an SMI# handler to an SCI
handler. This bit remains set until a 1 is written to this bit position.
Once a 1 is written to this bit position, the logic will “re-arm” to allow the bit to be set
on the next write of ‘1’ to SCI_NOW_CNT (Offset B1h:Bit 8).
QRT_PB_SCI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from
high to low (post-debounce). It can be enabled to cause an SCI which will allow the
QRT software to see when the power button has been pressed. It is a separate bit from
PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide any
indication to other (i.e. QRT) software.
The QRT software clears QRT_PB_SCI_STS by writing a 1 to this bit position.
Reserved
QRT_PB_SMI_STS — R/WC: This bit goes active when the PWRBTN# pin goes from
high to low (post-debounce). It can be enabled to cause an SMI# which will allow the
QRT software to see when the power button has been pressed. It is a separate bit from
PWRBTN_STS because the OS clears the PWRBTN_STS bit and does not provide any
indication to other (i.e. QRT) software.
The QRT software clears QRT_PB_SMI_STS by writing a 1 to this bit position.
Reserved.
ICH8DH Only)
00000000h
00h
No
Resume
Attribute:
Size:
Usage:
Description
Description
Attribute:
Size:
R/W
8-bit
Quick Resume Technology
R/W, R/WL
32-bit
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