NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 558

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.2
13.2.3
558
BMIS[P,S]—Bus Master IDE Status Register (D31:F5)
Address Offset: Primary: BAR + 02h
Default Value:
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5)
Address Offset: Primary: BAR + 04h–07h
Default Value:
31:2
4:3
Bit
1:0
Bit
7
6
5
2
1
0
PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit
Reserved.
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
Reserved. Returns 0.
Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH8 when the last transfer for a region is performed,
1 = Set by the ICH8 when the Start bit is written to the Command register.
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
Table must be DWord-aligned. The Descriptor Table must not cross a 64-KB boundary in
memory.
Reserved
set.
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The ICH8 does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
disabled interrupts via the IEN bit of the Device Control Register (see chapter 5 of
the Serial ATA Specification, Revision 2.5).
transferring data on PCI.
where EOT for that region is set in the region descriptor. It is also cleared by the
ICH8 when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
Secondary: BAR + 0Ah
00h
Secondary: BAR + 0Ch
All bits undefined
–
Description
0Fh
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F5)
R/W, R/WC, RO
8 bits
R/W
32 bits
Intel
®
ICH8 Family Datasheet