NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 193

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Table 80.
5.15.2.5
Intel
®
ICH8 Family Datasheet
The last PRD in a table has the End of List (EOL) bit set. The PCI bus master data
transfers terminate when the physical region described by the last PRD in the table has
been completely transferred. The active bit in the Status Register is reset and the
DDRQ signal is masked.
The buffer is flushed (when in the write state) or invalidated (when in the read state)
when a terminal count condition exists; that is, the current region descriptor has the
EOL bit set and that region has been exhausted. The buffer is also flushed (write state)
or invalidated (read state) when the Interrupt bit in the Bus Master IDE Status register
is set. Software that reads the status register and finds the Error bit reset, and either
the Active bit reset or the Interrupt bit set, can be assured that all data destined for
system memory has been transferred and that data is valid in system memory.
Table 80
after a DMA transfer has started.
Interrupt/Active Bit Interaction Definition
Error Conditions
IDE devices are sector based mass storage devices. The drivers handle errors on a
sector basis; either a sector is transferred successfully or it is not. A sector is
512 bytes.
If the IDE device does not complete the transfer due to a hardware or software error,
the command will eventually be stopped by the driver setting Command Start bit to 0
when the driver times out the disk transaction. Information in the IDE device registers
help isolate the cause of the problem.
If the controller encounters an error while doing the bus master transfers it will stop
the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in
the Bus Master IDE Status register. The controller does not generate an interrupt when
this happens. The device driver can use device specific information (PCI Configuration
Space Status register and IDE Drive Register) to determine what caused the error.
Whenever a requested transfer does not complete properly, information in the IDE
device registers (Sector Count) can be used to determine how much of the transfer was
completed and to construct a new PRD table to complete the requested operation. In
most cases the existing PRD table can be used to complete the operation.
Interrupt
0
1
1
0
describes how to interpret the Interrupt and Active bits in the Status Register
Active
1
0
1
0
DMA transfer is in progress. No interrupt has been generated by the IDE
device.
The IDE device generated an interrupt. The controller exhausted the
Physical Region Descriptors. This is the normal completion case where
the size of the physical memory regions was equal to the IDE device
transfer size.
The IDE device generated an interrupt. The controller has not reached
the end of the physical memory regions. This is a valid completion case
where the size of the physical memory regions was larger than the IDE
device transfer size.
This bit combination signals an error condition. If the Error bit in the
status register is set, then the controller has some problem transferring
data to/from memory. Specifics of the error have to be determined using
bus-specific information. If the Error bit is not set, then the PRDs
specified a smaller size than the IDE transfer size.
Description
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