NH82801HBM S LB9A Intel, NH82801HBM S LB9A Datasheet - Page 169

• Manufacturer Part Number: NH82801HBM S LB9A
• Description: CONTROLLER HUB, ICH8M, I/O, 82801HBM
• Manufacturer: Intel

Specifications of NH82801HBM S LB9A

• Power Dissipation Pd: 2.4W
• Digital Ic Case Style: BGA
• No. Of Pins: 676
• Pci Bus Type: I/O Controller Hub
• Pci Express Base Spec: PCIe 1.1
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
5.13.6.4
5.13.6.5
5.13.7
5.13.7.1
5.13.7.2
Intel
®
ICH8 Family Datasheet
Conditions for Re-Starting the PCI Clock
If an internal source requests the clock to be re-started, the ICH8 re-asserts CLKRUN#,
and simultaneously deasserts the STP_PCI# signal.
LPC Devices and CLKRUN#
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC
serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus
master cycles will not need to assert CLKRUN#, since the ICH8 asserts it on their
behalf.
The LDRQ# inputs are ignored by the ICH8 when the PCI clock is stopped to the LPC
devices in order to avoid misinterpreting the request. The ICH8 assumes that only one
more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#.
Upon deassertion of STP_PCI#, the ICH8 assumes that the LPC device receives its first
clock rising edge corresponding to the ICH8’s second PCI clock rising edge after the
deassertion.
Sleep States
Sleep State Overview
The ICH8 directly supports different sleep states (S1–S5), which are entered by setting
the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states is based
on several assumptions:
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the ICH8 observes the CLKRUN# signal asserted for 1 (free running) clock,
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
• Prior to setting the SLP_EN bit, the software turns off processor-controlled
• The G3 state cannot be entered via any software mechanism. The G3 state
• Masking interrupts, turning off all bus master enable bits, setting the desired type
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can
the ICH8 deasserts the STP_PCI# signal to the clock synthesizer within 4 (free
running) clocks.
ICH8 again starts driving CLKRUN# asserted.
the processor can only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit disables thermal throttling (since S1–S5 sleep state has higher priority).
indicates a complete loss of power.
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on observing Stop-Grant cycles from the processor or
on clocks other than the RTC clock
occur when system is in S0 or S1 state.
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